Renesas SH7781 - Manual (Page 99)

4. Pipelining
Rev.1.00 Jan. 10, 2008 Page 69 of 1658
REJ09B0261-0100
I1 I2 I3 ID S1 S2 S3 WB
I3
I3
I3
I3
I1 I2 ID S1 S2 S3 WB
I1 I2 ID S1 S2 S3 WB
E2S2 E3S3 WB E1S1
I1 I2 ID S1 S2 S3 WB
E2S2 E3S3 WB E1S1
E2S2 E3S3 WB E1S1
E2s2 E3s3 E1s1 I1 I2 ID WB
I1 I2 I3 ID s1 s2 s3 WB
I1 I2 I3 ID S1 S2 S3 WB
I3
I3
I1 I2 ID S1 S2 S3 WB
I1 I2 ID S1 S2 S3 WB
S1 S2 S3 WB
ID
ID
ID
ID
ID
E1s1 E2s2 E3s3 WB ID
E1s1
E1s1
E1s1
E2s2
E2s2
E2s2
E3s3
E3s3
E3s3
WB
WB
WB
(I1) (ID) (I2) (I3)
I1 I2 I3 ID s1 s2 s3 WB
E1s1
E1s1
E1s1
E2s2
E2s2
E2s2
E3s3
E3s3
E3s3
WB
WB
WB
(I1) (ID) (I2) (I3)
ID
ID
ID
ID
ID
ID
ID
ID
ID
ID
(3-1) Load/store: 1 issue cycle
(3-2) AND.B, OR.B, XOR.B, TST.B: 3 issue cycles
(3-3) TAS.B: 4 issue cycles
(3-4) PREF, OCBI, OCBP, OCBWB, MOVCA.L, SYNCO: 1 issue cycle
MOV.[BWL], MOV.[BWL] @(d,GBR)
(3-5) LDTLB: 1 issue cycle
(3-6) ICBI: 8 issue cycles + 5 cycles + 4 branch cycle
(3-7) PREFI: 5 issue cycles + 5 cycles + 4 branch cycle
(3-8) MOVLI.L: 1 issue cycle
(3-9) MOVCO.L: 1 issue cycle
(3-10) MOVUA.L: 2 issue cycles
(Branch to the next instruction of ICBI.)
5 cycles (min.)
(Branch to the next instruction of PREFI.)
5 cycles (min.)
Figure 4.2 Instruction Execution Patterns (3)