Renesas SH7781 - Manual (Page 410)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 380 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
11
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
10 to 8 WTH 111 R/W
WE Hold Cycle (WE Negation–CSn Negation Delay
Cycle)
These bits specify the number of cycles to be inserted
as the time from
WE negation to CSn negation. (Only
valid when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted (0.5 cycle delayed)
001: 1 cycle inserted (1.5 cycles delayed)
010: 2 cycles inserted (2.5 cycles delayed)
011: 3 cycles inserted (3.5 cycles delayed)
100: 4 cycles inserted (4.5 cycles delayed)
101: 5 cycles inserted (5.5 cycles delayed)
110: 6 cycles inserted (6.5 cycles delayed)
111: 7 cycles inserted (7.5 cycles delayed)
7
⎯ 0
R Reserved
This bit is always read as 0. The write value should
always be 0.
6 to 4 BSH 000 R/W
BS Hold Cycle
These bits specify the number of cycles to extend
BS
assertion. The extension of the assertion is valid when
the RDS bits in CSnWCR are not set to 000 in reading
and when the WTS bits in CSnWCR are not set to 000
in writing
. The total access cycle count is not changed
by setting these bits.
000:
BS assertion is 1 cycle
001:
BS assertion is 2 cycles
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited