Renesas SH7781 - Manual (Page 692)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 662 of 1658
REJ09B0261-0100
(3) Address/Data Stepping Timing
By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the
PCIC is driving the AD bus. As a result, the PCIC drives the AD bus with 2 clocks. This function
can be used when the PCI bus load is heavy and the AD bus does not achieve the stipulated logic
level in one clock.
It is recommended to use this function when the PCIC issues configuration transfers in host mode.
Figure 13.27 shows an example of a burst memory write cycle with address stepping. Figure 13.28
shows an example of a target burst read cycle with address stepping.
Addr D0
AP DP0
Com BE0
Dn
DPn-1 DPn
BEn
PCICLK
AD[31:0]
PAR
C/ BE[3:0]
PCIFRAME
IRDY
DEVSEL
TRDY
Legend:
Addr: PCI space address
Dn: nth data
AP: Address parity
DPn: nth data parity
Com: Command
BEn: nth data byte enable
Figure 13.27 Master Write Cycle in Host Mode (Burst, with Stepping)