Renesas SH7781 User Manual

Page 881

19. Display Unit (DU)

Rev.1.00 Jan. 10, 2008 Page 851 of 1658

REJ09B0261-0100

Bit Bit

Name

Initial
Value R/W

Internal
Update Description

DFB1

None

Display Frame Buffer 1 Flag

0: The address indicated by the plane 1 display

area start address 0 register (P1DSA0R) in
plane 1 is being used as the display area start
address

1: The address indicated by the plane 1 display

area start address 0 register (P1DSA1R) in
plane 1 is being used as the display area start
address

TVR

None

TV Synchronization Error Flag

0: After using the DRES bit in DSYSR or the

TVCL bit in the display status register clear
register (DSRCR) to clear the TVR bit to 0,
indicates that the rising edge of EXVSYNC is
being detected each time within the vertical
period determined by the setting of the
vertical scan period register (VCR).

1: Indicates that the rising edge of EXVSYNC

was not detected within the vertical period
determined by the setting of VCR when in TV
sync mode.
The TVR bit holds its state until cleared to 0
by the DRES bit in DSYSR or by the TVCL bit
in DSRCR.

14 FRM 0 R

None

Frame

Flag

0: After clearing to 0 the FRM bit using either the

DRES bit in DSYSR or the FRCL bit in
DSRCR, in interlaced mode indicates the
interval to the next display end, and in
interlaced sync mode or in interlaced sync &
video mode indicates the interval to the
display end of the next even field.

1: After clearing to 0 the FRM bit using either the

DRES bit in DSYSR or the FRCL bit in
DSRCR, indicates the interval until the next
time the FRM bit is cleared, from the first
vertical blanking interval in non-interlaced
mode, and from the first even field blanking
interval in interlaced sync or in interlaced sync
& video mode. (frame units)