Renesas SH7781 - Manual (Page 876)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 846 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Internal
Update Description
24 CSPM 0 R/W * CSYNC Pin Mode
Settings in DSYSR are given priority over
settings in this register.
0: CSYNC signal is output to the
HSYNC pin
1: HSYNC signal is output to the
HSYNC pin
23 to 20
⎯ All
0 R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
19 DIL 0 R/W * DISP Polarity Select
0: DISP signal at high level during display
interval
1: DISP signal at low level during display interval
18 VSL 0 R/W * VSYNC Polarity Select
0: VSYNC signal is low-active
1: VSYNC signal is high-active
17 HSL 0 R/W * HSYNC Polarity Select
0: HSYNC signal is low-active
1: HSYNC signal is high-active
16 DDIS 0 R/W * DISP Output Disable
0: DISP signal is output
1: DISP signal is not output (fixed to low level)
15 CDEL 0 R/W * CDE Polarity Select
0: CDE signal is high when output display data
and the color detection register (CDER)
match, and is low when they do not match
1: CDE signal is low when output display data
and CDER match, and is high when they do
not match