Renesas SH7781 - Manual (Page 1064)

21. Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Jan. 10, 2008 Page 1034 of 1658
REJ09B0261-0100
• Full-duplex communication capability
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling continuous
transmission and reception of serial data.
• LSB first for data transmission and reception
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of clock source: internal clock from baud rate generator or external clock from
SCIF0_SCK to SCIF5_SCK pins
• Four interrupt sources
There are four interrupt sources – transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive error – that can issue requests independently.
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
• When not in use, the SCIF can be stopped by halting its clock supply to reduce power
consumption.
• In asynchronous mode, modem control functions (SCIF0_RTS and SCIF0_CTS) are
provided.(only in channel 0)
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
the receive data in the receive FIFO register, can be ascertained.
• In asynchronous mode, a timeout error (DR) can be detected during reception.