Renesas SH7781 - Manual (Page 188)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 158 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
25, 24
⎯ All
0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
23 to 18 URB 000000 R/W UTLB Replace Boundary
These bits indicate the UTLB entry boundary at which
replacement is to be performed. Valid only when URB
≠
0.
17, 16
⎯ All
0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
15 to 10 URC 000000 R/W UTLB Replace Counter
These bits serve as a random counter for indicating the
UTLB entry for which replacement is to be performed
with an LDTLB instruction. This bit is incremented each
time the UTLB is accessed. If URB
> 0, URC is cleared
to 0 when the condition URC = URB is satisfied. Also
note that if a value is written to URC by software which
results in the condition of URC
> URB, incrementing is
first performed in excess of URB until URC = H'3F.
URC is not incremented by an LDTLB instruction.
9 SQMD 0 R/W Store Queue Mode
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception
in case of user access)
8 SV 0 R/W Single Virtual Memory Mode/Multiple Virtual Memory
Mode Switching
When this bit is changed, ensure that 1 is also written
to the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode