Renesas SH7781 - Manual (Page 274)

9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 244 of 1658
REJ09B0261-0100
(2) IL Memory
• Capacity
The IL memory in this LSI is 8 Kbytes.
• Page
The IL memory is divided into two pages (pages 0 and 1).
• Memory map
The IL memory is allocated to the addresses shown in table 9.2 in both the virtual address
space and the physical address space.
Table 9.2 IL Memory Addresses
Page Memory Address
Page 0 H'E520 0000 to H'E520 0FFF
Page 1
⎯
• Ports
The page has three independent read/write ports and is connected to the SuperHyway bus, the
cache/RAM internal bus, and the instruction bus. The instruction bus is used when the IL
memory is accessed through instruction fetch. The cache/RAM internal bus is used when the
IL memory is accessed through operand access. The SuperHyway bus is used for IL memory
access from the SuperHyway bus master module.
• Priority
In the event of simultaneous accesses to the same page from different buses, the access
requests are processed according to priority. The priority order is: SuperHyway bus >
cache/RAM internal bus > instruction bus.
(3)
U Memory
• Capacity
The U memory in this LSI is 128 Kbytes.
• Access method
Instruction fetch and operand write access are performed via the cache/RAM internal bus.
Operand read access is optimized for sequential operand access by using the read buffer.
• Memory map
The U memory is allocated to the addresses shown in table 9.3 in both the virtual address
space and the physical address space.