Renesas SH7781 - Manual (Page 466)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 436 of 1658
REJ09B0261-0100
D2 D1
Tm1
CLKOUT
A
RD/FRAME
CSn
R/ W
D63 to D0
BS
Tmd1w Tmd1 Tmd2w Tmd2 Tmd3 Tmd4w Tmd4
RDY
DACKn
D0 D3
In this example, DACKn is active-high.
Figure 11.31 MPX Interface Timing 8 (Burst Write Cycle, IW
= 0001,
External Wait Control, 32-Bit Bus Width, 32-Byte Data Transfer)