Renesas SH7781 - Manual (Page 1607)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1577 of 1658
REJ09B0261-0100
A25 to A0
D31 to D0
D31 to D0
(Write)
(Read)
(SA: IO ← memory)
(SA: IO → memory)
Legend:
IO: DACK
device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
t
WDD
t
WDD
t
WDD
t
DACDF
t
DACDF
CLKOUT
RD/ WR
RD
CSn
RDY
BS
WEn
DACKn
(DA)
T1
t
AD
Tw Twe T2
t
AD
t
RDH
t
RDS
t
CSD
t
RWD
t
RWD
t
CSD
t
RSD
t
RSD
t
RSD
t
WED1
t
WEDF
t
WEDF
t
RDYH
t
RDYS
t
RDYH
t
RDYS
t
BSD
t
BSD
t
DACD
t
DACD
t
DACD
t
DACD
t
DACD
DACKn
DACKn
Figure 32.11 SRAM Bus Cycle: Basic Bus Cycle
(One Internal Wait Cycle + One External Wait Cycle)