Renesas SH7781 - Manual (Page 387)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 357 of 1658
REJ09B0261-0100
11.3.2 Memory Bus Width
The memory bus width of the LBSC can be set independently for each area. In area 0, a bus width
of 8, 16, 32, or 64 bits is selected according to the external pin settings at a power-on reset by the
PRESET pin. The relation between the external pins (MODE 6 and MODE 5) and the bus width at
a power-on reset is shown below.
MODE6 MODE5 Bus Width
0 0 64 bits
0 1 8 bits
1 0 16 bits
1 1 32 bits
Note: When using 64 bits bus width, the MODE 12 and MODE11 must be set to 1 and 0
respectively.
By setting MODE12 and MODE11 to 1 and 0 respectively, D63 to D32 and
WE7 and WE4 can be
used in the LBSC. When 64-bit bus is used, set MODE12 and MODE11 to 1 and 0 respectively.
The relationship between MODE12 and MODE11 and bus mode is shown below.
MODE12 MODE11 Bus Mode (D[63:32] and
WE[7:4])
0 0 PCI (host)
0 1 PCI (normal)
1 0 LBSC
1 1 DU
When the SRAM or ROM interface is used in areas 0 to 6, a bus width of 8, 16, 32, or 64 bits can
be selected by the CSn bus control register (CSnBCR). When the burst ROM interface is used, a
bus width of 8, 16, 32, or 64 bits can be selected. When the byte control SRAM interface is used, a
bus width of 16, 32, or 64 bits can be selected. When the MPX interface is used, the bus width
should be set to 32 or 64 bits.
When the PCMCIA interface is used, the bus width should be set to 8 or 16 bits. For details, see
section 11.5.5, PCMCIA Interface.
For details of memory bus width, see section 11.4.3, CSn Bus Control Register (CSnBCR).
The address range of area 7, from H'1C00 0000 to H'1FFFF FFFF, is reserved and must not be
used.