Renesas SH7781 - Manual (Page 870)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 840 of 1658
REJ09B0261-0100
Register Name Abbr.
Power-On
Reset by
PRESET
Pin/ WDT/
H-UDI
Manual
Reset by
WDT Sleep by
Sleep
Instruction
Module
Standby Deep
Sleep
Bits with
Internal Update
Function
Color palette 3
register 000 CP3_000R Undefined Retained Retained Retained Retained All bits
⎯
Color palette 3
register 255 CP3_255R Undefined Retained Retained Retained Retained All bits
Color palette 4
register 000 CP4_000R Undefined Retained Retained Retained Retained All bits
⎯
Color palette 4
register 255 CP4_255R Undefined Retained Retained Retained Retained All bits
External synchronization control register
External
synchronization
control register ESCR H'00000000 Retained Retained Retained Retained None
Output signal
timing adjustment
register OTAR H'00000000 Retained Retained Retained Retained These bits are
updated by the
DRES bit in
DSYSR.