Renesas SH7781 - Manual (Page 32)

1. Overview
Rev.1.00 Jan. 10, 2008 Page 2 of 1658
REJ09B0261-0100
Item Features
CPU
• Renesas Technology original architecture
• 32-bit internal data bus
• General-register files:
⎯ Sixteen 32-bit general registers (eight 32-bit shadow registers)
⎯ Seven 32-bit control registers
⎯ Four 32-bit system registers
• RISC-type instruction set (upward compatibility for the SH-1, SH-2, SH-3
and SH-4 processors)
⎯ Instruction length: 16-bit fixed length for improved code efficiency
⎯ Load/store architecture
⎯ Delayed branch instructions
⎯ Conditional instruction execution
⎯ Instruction-set design based on the C language
• Super-scalar architecture covering both the FPU and CPU provides for
the simultaneous execution of any two instructions
• Instruction-execution time: Two instructions per cycle (max.)
• Virtual address space: 4 Gbytes
• Address-space identifiers (ASID): 8 bits, for 256 virtual address spaces
• Internal multiplier
• Eight-stage pipeline
• PVR.VER = H'30: SH-4A extended version