Renesas SH7781 - Manual (Page 1511)

29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1481 of 1658
REJ09B0261-0100
29.5 User Break Examples
(1) Match Conditions Are Specified for an Instruction Fetch Cycle
• Example 1-1
Register settings: CBR0 = H'00000013 / CRR0 = H'00002003 / CAR0 = H'00000404 /
CAMR0 = H'00000000 / CBR1 = H'00000013 / CRR1 = H'00002001 / CAR1 = H'00008010 /
CAMR1 = H'00000006 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H'00000000 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
⎯ Channel 0
Address: H'00000404 / Address mask: H'00000000
Bus cycle: Instruction fetch (after executing the instruction)
ASID is not included in the conditions.
⎯ Channel 1:
Address: H'00008010 / Address mask: H'00000006
Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000
Bus cycle: Instruction fetch (before executing instruction)
ASID, data values, and execution count are not included in the conditions.
With the above settings, the user break occurs after executing the instruction at address
H'00000404 or before executing the instruction at address H'00008010 to H'00008016.
• Example 1-2
Register settings: CBR0 = H'40800013 / CRR0 = H'00002000 / CAR0 = H'00037226 /
CAMR0 = H'00000000 / CBR1 = H'C0700013 / CRR1 = H'00002001 / CAR1 = H'0003722E /
CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H'00000000 / CBCR = H'00000000
Specified conditions: Channel 0
→ Channel1 sequential mode
⎯ Channel 0
Address: H'00037226 / Address mask: H'00000000 / ASID: H'80
Bus cycle: Instruction fetch (before executing the instruction)
⎯ Channel 1
Address: H'0003722E / Address mask: H'00000000 / ASID: H'70
Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000
Bus cycle: Instruction fetch (before executing the instruction)
Data values and execution count are not included in the conditions.