Renesas SH7781 - Manual (Page 629)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 599 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
9 TMTOI 0 SH: R/WC
PCI: R
Target Memory Read Retry Timeout Interrupt
Indicates that the master did not perform retry
processing within 2
15 clocks in PCICLK when the
PCIC is a target. This bit is detected only for memory
read transfers.
0: A target memory read retry timeout interrupt was
not generated
1: A target memory read retry timeout interrupt was
generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
8 MDEI 0 SH: R/WC
PCI: R
Master Function Disable Error Interrupt
Indicates that the PCIC attempted to operate as a
master (PIO or DMA transfer) although bit 2 (BM) in
PCICMD is cleared to 0 and operation as a bus
master is disabled.
0: A master function disable error interrupt was not
generated
1: A master function disable error interrupt was
generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
7 APEDI 0 SH: R/WC
PCI: R
Address Parity Error Detection Interrupt
Indicates that an address parity error was detected.
Note: An address parity error is detected only when
both of the bits 8 (SERRE) and 6 (PER) in
PCICMD are set to 1.
0: An address parity error interrupt was not
generated
1: An address parity error interrupt was generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.