Renesas SH7781 - Manual (Page 1401)

27. NAND Flash Memory Controller (FLCTL)
Rev.1.00 Jan. 10, 2008 Page 1371 of 1658
REJ09B0261-0100
27.4.4 Status Read
The FLCTL can read the status register of a NAND-type flash memory. The data in the status
register of a NAND-type flash memory is input through the I/O7 to I/O0 pins and stored in the bits
STAT7 to STAT0 in FLBSYCNT. The bits STAT7 to STAT0 in FLBSYCNT can be read by the
CPU. If a program error or erase error is detected when the status register value is stored in the
bits STAT7 to 0 in FLBSYCNT, the STERB bit in FLINTDMACR is set to 1 and generates an
interrupt to the CPU if the STERINTE bit in FLINTDMACR is enabled.
(1) Status Read of NAND-Type Flash Memory (512 + 16 Bytes)
The status read of NAND-type flash memory can be performed by inputting the command H'70 to
NAND-type flash memory. When the DOSR bit in FLCMDCR is set to 1 and writing is performed
in command access mode or sector access mode, the FLCTL automatically inputs H'70 to NAND-
type flash memory and status read is performed. During the status read of NAND-type flash
memory, the I/O7 to I/O0 pins indicate the following information as shown in table 27.4.
Table 27.4 Status Read of NAND-Type Flash Memory (512
+ 16 Bytes)
I/O Status (Definition) Description
I/O7 Write protection 0: Cannot be written
1: Can be written
I/O6 Ready/busy 0: Busy state
1: Ready state
I/O5 to I/O1 Reserved
⎯
I/O0 Write/erase 0: Pass
1: Fail