Renesas SH7781 - Manual (Page 529)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 499 of 1658
REJ09B0261-0100
12.4.8 SDRAM Refresh Control Register 0 (DBRFCNT0)
The SDRAM refresh control register 0 (DBRFCNT0) is a readable/writable register. It is
initialized only upon power-on reset.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ARFEN ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SRFEN
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W
Description
31 to 17
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
16 ARFEN 0 R/W Auto-Refresh Enable Bit
Enables or disables automatic issue of auto-refresh.
The auto-refresh command is issued periodically
according to the settings of DBRFCNT1/2.
For details on the auto-refresh command issue timing,
refer to section 12.5.5, Auto-Refresh Operation.
0: Disables automatic issue of auto-refresh.
1: Enables automatic issue of auto-refresh.
15 to 1
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.