Renesas SH7781 - Manual (Page 1144)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1114 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
9 RFFUL 0 R Receive FIFO Full
0: Receive FIFO not full
1: Receive FIFO full
• This bit is valid when the RXE bit in SICTR is 1.
• This bit indicates the state of the SIOF. If SIRDR is
read from, this bit is automatically cleared to 0.
• To enable the issuance of this interrupt source, set
the RFFULE bit in SIIER to 1.
8 RDREQ 0 R Receive Data Transfer Request
0: Indicates that the size of valid space in the receive
FIFO does not exceed the size specified by the
RFWM bit in SIFCTR.
1: Indicates that the size of valid space in the receive
FIFO exceeds the size specified by the RFWM bit in
SIFCTR.
A receive data transfer request is issued when the valid
space in the receive FIFO exceeds the value specified
by the RFWM bit in SIFCTR.
When using receive data transfer through the DMAC,
this bit is always cleared by one DMAC access. After
DMAC access, when conditions for setting this bit are
satisfied, this bit is set to 1 again by the SIOF.
• This bit is valid when the RXE bit in SICTR is 1.
• This bit indicates a state; if the size of valid data
space in the receive FIFO is less than the size
specified by the RFWM bit in SIFCTR, this bit is
automatically cleared to 0.
• To enable the issuance of this interrupt source, set
the RDREQE bit in SIIER to 1.
7, 6
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.