Renesas SH7781 User Manual

Page 202

7. Memory Management Unit (MMU)

Rev.1.00 Jan. 10, 2008 Page 172 of 1658
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EPR[1]: Writing in user mode

EPR[0]: Execution in user mode (instruction fetch)

• C: Cacheability bit

Indicates whether a page is cacheable.

0: Not cacheable

1: Cacheable

When the control register area is mapped, this bit must be cleared to 0.

• D: Dirty bit

Indicates whether a write has been performed to a page.

0: Write has not been performed.

1: Write has been performed.

• WT: Write-through bit

Specifies the cache write mode.

0: Copy-back mode

1: Write-through mode