Renesas SH7781 - Manual (Page 530)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 500 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
0 SRFEN 0 R/W Self-Refresh Mode Bit
Performs transition to or cancellation of self-refresh
mode. By writing 1, a transition is made to self-refresh.
By writing 0, self-refresh mode is cancelled. For details
on transition to or cancellation of self-refresh, refer to
section 12.5.4, Self-Refresh Operation.
0: Cancels self-refresh.
1: Makes a transition to self-refresh.
12.4.9 SDRAM Refresh Control Register 1 (DBRFCNT1)
The SDRAM refresh control register 1 (DBRFCNT1) is a readable/writable register. It is
initialized only upon power-on reset.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R R R R R R R R R R R R R R R R
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
TREFI0 TREFI1 TREFI2 TREFI3 TREFI4 TREFI5 TREFI6 TREFI7 TREFI8 TREFI9 TREFI10 TREFI11 TREFI12
⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W
Description
31 to 13
⎯
All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.