Renesas SH7781 - Manual (Page 1005)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 975 of 1658
REJ09B0261-0100
Table 20.2 GDTA Register Configuration (CL Block)
Name Abbreviation R/W P4 Address
Area 7
Address Access
Size Sync
Clock
CL command FIFO CLCF W H'FE40 1000 H'1E40 1000 32 GAck
CL control register CLCR R/W H'FE40 1004 H'1E40 1004 32 GAck
CL status register CLSR R H'FE40 1008 H'1E40 1008 32 GAck
CL frame width setting
register CLWR R/W H'FE40 100C H'1E40 100C 32 GAck
CL frame height setting
register CLHR R/W H'FE40 1010 H'1E40 1010 32 GAck
CL input Y padding size
setting register CLIYPR R/W H'FE40 1014 H'1E40 1014 32 GAck
CL input UV padding
size setting register CLIUVPR R/W H'FE40 1018 H'1E40 1018 32 GAck
CL output padding size
setting register CLOPR R/W H'FE40 101C H'1E40 101C 32 GAck
CL palette pointer setting
register CLPLPR R/W H'FE40 1020 H'1E40 1020 32 GAck