Renesas SH7781 - Manual (Page 43)

1. Overview
Rev.1.00 Jan. 10, 2008 Page 13 of 1658
REJ09B0261-0100
1.2 Block Diagram
A block diagram of the SH7785 is given as figure 1.1.
ROM
NOR Flash
PC Card/ATA3
DDR2-SDRAM
DDR2-400/600
1 GB max
SH-4A
Superscalar CPU
FPU
MMU
32 KB I-cache
32 KB O-cache
8 KB ILRAM
16 KB OLRAM
32 bit/16 bit
300 MHz
32 bit
33/66 MHz
PCI bus
64*/32/16
/8 bit
100 MHz Local Bus
Controller
SRAM, ROM,
PCMCIA
MPX
SCIF0/HSPI/FLCTL
Periperal bus Super Hyway
CPG
TMU, WDT
SRAM
PCI
Controller
HAC/SSI/SIOF
DMA
Controller
INTC
Debug
GDTA
SCIF2/MMCIF
Display Unit
Peripheral Bus Controller
DDR bus
Local bus
DDRII-SDRAM
Controller
(DBSC)
URAM
128 KB
HAC/SSI
Note: * The PCI bus and the display unit are not available when the local bus width is 64 bits.
The PCI controller and the display unit cannot be used when the local bus width is 64 bits.
Figure 1.1 SH7785 Block Diagram