Renesas SH7781 - Manual (Page 490)

12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 460 of 1658
REJ09B0261-0100
12.2 Input/Output Pins
Table 12.1 shows the pin configuration of the DBSC2.
Table 12.1 Pin Configuration of the DBSC2
Pin Name Function I/O Description
MCK0 DDR2-SDRAM clock 0 Output Clock output for the DDR2-SDRAM
MCK0
DDR2-SDRAM clock 0 Output Clock output for the DDR2-SDRAM or
MCK0 inverted clock output
MCK1 DDR2-SDRAM clock 1 Output Clock output for the DDR2-SDRAM
MCK1
DDR2-SDRAM clock 1 Output Clock output for the DDR2-SDRAM or
MCK1 inverted clock output
MCKE Clock enable Output CKE output signal
MCS
Chip select Output Chip select output signal
MWE
Write enable Output Write enable output signal
MRAS
Row address strobe Output Row address strobe output signal
MCAS
Column address strobe Output Column address strobe output signal
MA14 to MA0 Addresses Output Address output signals
MBA2, MBA1,
MBA0 Bank active Output Bank address output signal
MDQ31 to
MDQ0 Data I/O Data I/O signals
MDQS3 to
MDQS0 I/O data strobe I/O Data strobe I/O signals
MDQS3 to
MDQS0
I/O data strobe I/O Data strobe I/O signals or MDQS3 to
MDQS0 inverted signals
MDM3 to
MDM0 Data mask Output Data mask output signals
MODT ODT enable Output ODT enable output signal to the SDRAM
MBKPRST
Power backup reset Input Used in power backup mode.
When this pin is brought low level, the
MCKE pin is also pulled low.
MVREF Reference voltage input Input Input reference voltage