Renesas SH7781 - Manual (Page 11)

Rev.1.00 Jan. 10, 2008 Page xi of xxx
REJ09B0261-0100
7.1.1 Address Spaces ................................................................................................... 146
7.2 Register Descriptions ......................................................................................................... 152
7.2.1 Page Table Entry High Register (PTEH) ............................................................ 153
7.2.2 Page Table Entry Low Register (PTEL) ............................................................. 154
7.2.3 Translation Table Base Register (TTB) .............................................................. 155
7.2.4 TLB Exception Address Register (TEA) ............................................................ 156
7.2.5 MMU Control Register (MMUCR) .................................................................... 156
7.2.6 Page Table Entry Assistance Register (PTEA)................................................... 159
7.2.7 Physical Address Space Control Register (PASCR)........................................... 160
7.2.8 Instruction Re-Fetch Inhibit Control Register (IRMCR) .................................... 162
7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)............................................ 164
7.3.1 Unified TLB (UTLB) Configuration .................................................................. 164
7.3.2 Instruction TLB (ITLB) Configuration............................................................... 167
7.3.3 Address Translation Method............................................................................... 167
7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1) ............................................... 170
7.4.1 Unified TLB (UTLB) Configuration .................................................................. 170
7.4.2 Instruction TLB (ITLB) Configuration............................................................... 173
7.4.3 Address Translation Method............................................................................... 174
7.5 MMU Functions................................................................................................................. 177
7.5.1 MMU Hardware Management............................................................................ 177
7.5.2 MMU Software Management ............................................................................. 177
7.5.3 MMU Instruction (LDTLB)................................................................................ 178
7.5.4 Hardware ITLB Miss Handling .......................................................................... 180
7.5.5 Avoiding Synonym Problems ............................................................................. 181
7.6 MMU Exceptions............................................................................................................... 182
7.6.1 Instruction TLB Multiple Hit Exception............................................................. 182
7.6.2 Instruction TLB Miss Exception......................................................................... 183
7.6.3 Instruction TLB Protection Violation Exception ................................................ 184
7.6.4 Data TLB Multiple Hit Exception ...................................................................... 185
7.6.5 Data TLB Miss Exception .................................................................................. 185
7.6.6 Data TLB Protection Violation Exception.......................................................... 187
7.6.7 Initial Page Write Exception............................................................................... 188
7.7 Memory-Mapped TLB Configuration................................................................................ 190
7.7.1 ITLB Address Array ........................................................................................... 191
7.7.2 ITLB Data Array (TLB Compatible Mode)........................................................ 192
7.7.3 ITLB Data Array (TLB Extended Mode) ........................................................... 193
7.7.4 UTLB Address Array.......................................................................................... 195
7.7.5 UTLB Data Array (TLB Compatible Mode) ...................................................... 196
7.7.6 UTLB Data Array (TLB Extended Mode).......................................................... 197
7.8 32-Bit Address Extended Mode ......................................................................................... 199