Section 22 serial i/o with fifo (siof), 1 features – Renesas SH7781 User Manual

Page 1129

22. Serial I/O with FIFO (SIOF)

Rev.1.00 Jan. 10, 2008 Page 1099 of 1658

REJ09B0261-0100

Section 22 Serial I/O with FIFO (SIOF)

This LSI is equipped with a clock-synchronized serial I/O module with FIFO (SIOF).

22.1

Features

• Serial transfer

32-bit FIFO

× 16-stage (the transmit FIFO and receive FIFO are independent units)

Supports input/output for 8-bit data, 16-bit data, and 16-bit stereo audio data

MSB first for data transmission and reception

Supports up to 48-kHz sampling rate

Synchronization by either frame synchronization pulse or left/right channel switch

Supports CODEC control data interface

Connectable to linear, audio, A-Law, or

μ-Law CODEC chip

Supports both master and slave modes

• Serial clock

An external pin input or peripheral clock (Pck) can be selected as the clock source.

• Interrupts: One type
• DMA transfer

Supports DMA transfer by a transfer request from the transmit FIFO unit