Renesas SH7781 - Manual (Page 423)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 393 of 1658
REJ09B0261-0100
Table 11.11 64-Bit External Device/Little Endian Access and Data Alignment (1)
Operation Data Bus
Access
Size Address No.
D63 to
D56
D55 to
D48
D47 to
D40
D39 to
D32
D31 to
D24
D23 to
D16 D15 to D8 D7 to D0
8n 1 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Data 7 to 0
8n
+ 1
1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Data 7 to 0
⎯
8n + 2 1 ⎯ ⎯ ⎯ ⎯ ⎯ Data 7 to 0 ⎯ ⎯
8n + 3 1 ⎯ ⎯ ⎯ ⎯ Data 7 to 0 ⎯ ⎯ ⎯
8n + 4 1 ⎯ ⎯ ⎯ Data 7 to 0 ⎯ ⎯ ⎯ ⎯
8n + 5 1 ⎯ ⎯ Data 7 to 0 ⎯ ⎯ ⎯ ⎯ ⎯
8n + 6 1 ⎯ Data 7 to 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Byte
8n
+ 7
1 Data 7 to 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8n 1
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Data
15 to
8
Data 7 to 0
8n + 2 1 ⎯ ⎯ ⎯ ⎯ Data 15 to
8
Data 7 to 0 ⎯ ⎯
8n + 4 1 ⎯ ⎯ Data 15 to
8
Data 7 to 0 ⎯ ⎯ ⎯ ⎯
Word
8n + 6 1 Data 15 to
8
Data 7 to 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
8n 1
⎯ ⎯ ⎯ ⎯ Data
31 to
24
Data 23 to
16
Data 15 to
8
Data 7 to 0 Longword
8n + 4 1 Data 31 to
24
Data 23 to
16
Data 15 to
8
Data 7 to 0 ⎯ ⎯ ⎯ ⎯
32 Bytes* 8n 1 Data 63 to
56
Data 55 to
48
Data 47 to
40
Data 39 to
32
Data 31 to
24
Data 23 to
16
Data 15 to
8
Data 7 to 0
8n + 8 2 Data 127
to 120
Data 119
to 112
Data 111
to 104
Data 103
to 96
Data 95 to
88
Data 87 to
80
Data 79 to
72
Data 71 to
64
8n + 16 3 Data 191
to 184
Data 183
to 176
Data 175
to 168
Data 167
to 160
Data 159
to 152
Data 151
to 144
Data 143
to 136
Data 135
to 128
8n + 24 4 Data 255
to 248
Data 247
to 240
Data 239
to 232
Data 231
to 224
Data 223
to 216
Data 215
to 208
Data 207
to 200
Data 199
to 192
Note: * This table shows an example when the access start address is on the 32-byte
boundary. When the start address is not on the 32-byte boundary, accesses are
performed up to immediately before the 32-byte boundary and the address is wrapped
around to the previous 32-byte boundary.