Renesas SH7781 - Manual (Page 618)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 588 of 1658
REJ09B0261-0100
(27) PCIPMCSR Bridge Support Extension Register (PCIPMCSRBSE)
This register supports the functions specific to the PCI bridge and is required for all PCI-to-PCI
bridges.
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
— — — — — — B2B3N
BPC
CEN
R R R R R R R R
Bit:
Initial value:
SH R/W:
R R R R R R R R PCI R/W:
Bit Bit Name
Initial
Value R/W
Description
7 BPCCEN 0 SH: R
PCI: R
When the bus power/clock control mechanism is
disabled, the system software does not use the power
state field in PCI_PMCSR of the bridge to control the
power or clock of the secondary bus of the bridge.
6 B2B3N 0 SH: R
PCI: R
The state of this bit determines the action to be taken
as a result of programming that sets the power
management function to the D3 hot state.
0: Indicates that the power supplied to the secondary
will be stopped (B3) when the bridge function is set
to the D3 hot state.
1: Indicates that the PCI clock of the secondary bus
will be stopped (B2) when the bridge function is set
to the D3 hot state.
This bit is valid only when bit 7 (PCI_BPCCEN) is set
to 1.
5 to 0
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.