Renesas SH7781 - Manual (Page 886)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 856 of 1658
REJ09B0261-0100
The following are conditions, based on DSSR and this register, for issuing an interrupt to the CPU
from the display unit (DU).
Conditions for issuing an interrupt
= a + b + c + d + e
• a = TVR · TVE
• b = FRM · FRE
• c = VBK · VBE
• d = RINT · RIE
• e = HBK · HBE
Interrupts from the display unit (DU) are reflected by bit 27 of the interrupt source register (not
affected by the mask state) (INT2A0) or by bit 27 of the interrupt source register (affected by the
mask state) (INT2A1) of the interrupt controller (INTC).