Renesas SH7781 - Manual (Page 1617)

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1587 of 1658
REJ09B0261-0100
Tm1 Tmd1w Tmd1
t
FMD
t
FMD
t
BSD
t
BSD
t
CSD
t
CSD
t
DACD
t
RDYH
t
RDYS
t
DACD
t
WED1
t
WED1
Tm1 Tmd1
t
FMD
t
FMD
t
BSD t
BSD
t
CSD
t
CSD
t
DACD
D0 D0
t
RDYH
t
RDYS
t
DACD
t
RWD
t
RWD
t
RWD
t
RWD
t
WED1
t
WED1
A
t
RDYH
t
RDYS
t
RDYH
t
RDYS
t
WDD
t
WDD
t
WDD
A
t
WDD
t
WDD
t
WDD
Tm1 Tmd1w Tmd1w Tmd1
t
FMD
t
FMD
t
BSD
t
BSD
t
CSD
t
CSD
t
DACD
t
DACD
t
WED1
t
WED1
D0
t
RWD
t
RWD
A
t
WDD
t
WDD
t
WDD
CLKOUT
RD/FRAME
RD/ WR
WEn
RDY
BS
CSn
DACKn
(DA)
D31 to D0
(1) 1st data: No wait
Information in the first data bus cycle
D31 to D29: Access size
000: Byte
001:
Word (2 bytes)
010: Longword (4 bytes)
011: Quadword (8 bytes)
1xx: Burst (32 bytes)
D25 to D0: Address
(2) 1st data: One internal wait cycle
Information in the first data bus cycle
D31 to D29: Access size
000: Byte
001:
Word (2 bytes)
010: Longword (4 bytes)
011: Quadword (8 bytes)
1xx: Burst (32 bytes)
D25 to D0: Address
(3) 1st data: One internal wait + one external wait cycles
Information in the first data bus cycle
D31 to D29: Access size
000: Byte
001:
Word (2 bytes)
010: Longword (4 bytes)
011: Quadword (8 bytes)
1xx: Burst (32 bytes)
D25 to D0: Address
Legend:
IO: DACK
device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
Figure 32.21 MPX Basic Bus Cycle (Write)