Renesas SH7781 - Manual (Page 1029)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 999 of 1658
REJ09B0261-0100
20.3.20 CL Palette Pointer Register (CLPLPR)
CLPLPR is in the CL register block and sets the color conversion table pointer. The RAM 0
address used for a work area should be specified. This register setting is used only in the ARBG
conversion mode, not used in the YUYV conversion mode.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CL_PLPT
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CL_PLPT
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 0 CL_PLPT All 0 R/W Palette Pointer Setting
An address in the range from H'FE41_0000 to
H'FE41_1FFF (P4 area address) should be specified.
Note: A 4-byte boundary address must be specified.