Renesas SH7781 - Manual (Page 776)

15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 746 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
19
18
17
16
BFST3
BFST2
BFST1
BFST0
x
x
x
1
R
R
R
R
Frequency division ratio of the bus clock (Bck)
0101:
Ч 1/12
0110:
Ч 1/16
0111:
Ч 1/18
1000:
Ч 1/24
1001:
Ч 1/32
1010:
Ч 1/36
1011:
Ч 1/48
15
14
13
12
MFST3
MFST2
MFST1
MFST0
0
0
1
x
R
R
R
R
Frequency division ratio of the DDR clock (DDRck)
0010:
Ч1/4
0011:
Ч1/6
11
10
9
8
S2FST3
S2FST2
S2FST1
S2FST0
0
1
0
x
R
R
R
R
Frequency division ratio of the GDTA clock (GAck)
0100:
Ч 1/8
0101:
Ч 1/12
1111: Stop the clock supply.
7
6
5
4
S3FST3
S3FST3
S3FST3
S3FST3
x
1
x
x
R
R
R
R
Frequency division ratio of the DU clock (DUck)
0100:
Ч 1/8
0101:
Ч 1/12
0110:
Ч 1/16
0111:
Ч 1/18
1000:
Ч 1/24
1001:
Ч 1/32
1010:
Ч 1/36
1011:
Ч 1/48
1111: Stop the clock supply
3
2
1
0
PFST3
PFST2
PFST1
PFST0
1
0
x
x
R
R
R
R
Frequency division ratio of the peripheral clock (Pck)
0111:
Ч 1/18
1000:
Ч 1/24
1001:
Ч 1/32
1010:
Ч 1/36
1011:
Ч 1/48