Figure 12.1 shows a block diagram of the dbsc2, Figure 12.1 block diagram of the dbsc2 – Renesas SH7781 User Manual

Page 489

12. DDR2-SDRAM Interface (DBSC2)

Rev.1.00 Jan. 10, 2008 Page 459 of 1658

REJ09B0261-0100

Figure 12.1 shows a block diagram of the DBSC2.

BUS IF

Request
queue

Control
unit

Registers

DDRPAD

DLL

IO cells

MDQS3 to MDQS0,

MDM3 to MDM0,
MDQ31 to MDQ0

MCKE, MA14 to MA0,
MBA2 to MBA0,

MCS,

MRAS, MCAS, MWE,
MODT

Write data
queue

Response
queue

SuperHyway Bus

DDR2-SDRAM

DBSC2

MCK0/
MCK0,
MCK1/
MCK1

MBKPRST, MVREF

Notes:
Request queue:
Write data queue:
Response queue:
Control unit:
Registers:
DDRPAD:

Stores the access request of the SuperHyway bus.
Stores the write data sent from the SuperHyway bus.
Stores the read data to be sent back to the SuperHyway bus.
Controls each block depending on the request sent from the request queue.
Store timing parameters and SDRAM configuration information.
Interfaces with the DDR2-SDRAM. This incorporates the DLL
to perform phase adjustment of the DQS.

Figure 12.1 Block Diagram of the DBSC2