Renesas SH7781 - Manual (Page 191)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 161 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
31 to 8
⎯ All
0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
7 to 0 UB H'00 R/W Buffered Write Control for Each Area (64 Mbytes)
When writing is performed without using the cache or in
the cache write-through mode, these bits specify
whether the next bus access from the CPU waits for the
end of writing for each area.
0 : Buffered write (The CPU does not wait for the end of
writing bus access and starts the next bus access)
1 : Unbuffered write (The CPU waits for the end of
writing bus access and starts the next bus access)
UB[7]: Corresponding to the control register area
UB[6]: Corresponding to area 6
UB[5]: Corresponding to area 5
UB[4]: Corresponding to area 4
UB[3]: Corresponding to area 3
UB[2]: Corresponding to area 2
UB[1]: Corresponding to area 1
UB[0]: Corresponding to area 0