Renesas SH7781 - Manual (Page 872)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 842 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Internal
Update Description
16 IUPD 0 R/W Yes Internal Updating Disable
When DRES = 1, internal update is performed
regardless of this bit.
For details of internal update, see (2) Internal
Update in section 19.3, Register Descriptions.
0: Internal update is performed upon each
vertical sync signal (VSYNC) assertion
1: By setting this bit to 1, internal updates can be
prohibited.
When this bit is set to 0, register update is
performed upon the next vertical sync signal
(VSYNC).
15 to 10
⎯ All
0 R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.