Renesas SH7781 - Manual (Page 206)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 176 of 1658
REJ09B0261-0100
Figure 7.15 is a flowchart of memory access using the ITLB in TLB extended mode.
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match,
ASIDs match, and
V = 1
Only one
entry matches
SR.MD?
Instruction TLB protection
violation exception
Instruction TLB
multiple hit exception
Instruction access to virtual address (VA)
VA is
in P4 area VA is
in P2 area VA is
in P1 area VA is in P0, U0,
or P3 area
Yes
Yes
No
No
No
Yes
Yes
1 (Privileged)
Search UTLB
0 (User)
Hardware ITLB
miss handling
Match?
MMUCR.AT = 1
Yes
No
Instruction TLB
miss exception
Memory access
(Non-cacheable)
Internal resource access
VPNs match
and V = 1
1
0
CCR.ICE?
Yes
No C = 1 and
CCR.ICE = 1
EPR[2] = 0 and
EPR[0] = 0
EPR[0]?
No
Record in ITLB
Yes
No
Yes
No
Yes
1 1
0 0
No
ICBI or normal instruction access?
ICBI Normal instruction access ICBI Normal instruction access
ICBI or normal instruction access?
EPR[5] = 0 and
EPR[3] = 0
EPR[3]?
Cache access
Figure 7.15 Flowchart of Memory Access Using ITLB (TLB Extended Mode)