Renesas SH7781 - Manual (Page 382)

11. Local Bus State Controller (LBSC)
Rev.1.00 Jan. 10, 2008 Page 352 of 1658
REJ09B0261-0100
Pin Name Function I/O Description
BACK
Bus Request
Acknowledge O Bus request acknowledge signal
Multiplexed with Port M0 (GPIO input/output).
CE2A* 1 ,
CE2B* 2
PCMCIA Card
Select O
CE2A , CE2B in PCMCIA interface setting
Only valid in little endian mode
CE2A: Multiplexed with DACK2 (DMAC output),
Port L5 (GPIO input/output)
CE2B: Multiplexed with MODE12, DACK3
(DMAC output) and Port L0 (GPIO
input/output)
MODE5,
MODE6,
MODE7 Bus Width and
Memory Type
for Area 0 I Signals for setting area 0 bus width (MODE5,
MODE6) and MPX interface (MODE7: high level
selects SRAM and low level selects MPX) at a
power-on reset by the
PRESET pin
MODE5: Multiplexed with SIOF_MCLK (SIOF
input)
MODE6: Multiplexed with SIOF_SYNC (SIOF
input/output)
MODE7: Multiplexed with SCIF3_RXD (SCIF
input) and FALE (FLCTL output)
MODE8 Endian
Switching
I Signal for setting endian at a power-on reset by
the
PRESET pin
Multiplexed with SCIF3_SCK (SCIF
input/output), FD0 (FLCTL input/output) and Port
N3 (GPIO output)
MODE9 Master/Slave
Switching
I Signal indicating master/slave at a power-on
reset by the
PRESET pin
Multiplexed with SCIF4_TXD (SCIF output), FD1
(FLCTL input/output) and Port N2 (GPIO output).