Renesas SH7781 - Manual (Page 636)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 606 of 1658
REJ09B0261-0100
(9) PCI Error Command Information Register (PCICIR)
This register records the PCI command information when an error is detected.
The value of this register is undefined until an interrupt is detected. Regardless of the information
on mask registers, etc, the value is retained when an interrupt is detected.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R R R R R R R R R R R R R R R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 x 0 0 0 x 0
— — — — — — — — — —
RW
TET
— — — MTEM —
R R R R R R R R R R R R R R R R
R R R R R R R R R R R R R R R R
x x x x 0 0 0 0 0 0 0 0 0 0 0 0
ECL — — — — — — — — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Description
31 MTEM x SH: R
PCI: R
Master Error
Indicates that an error occurred during a master read
or a master write transfer
0: No master error
1: Master error occurred
30 to 27
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
26 RWTET x SH: R
PCI: R
Target Error
Indicates that an error occurred during a target read
or a target write transfer.
0: No target error
1: Target error occurred
25 to 4
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
3 to 0 ECL xxxx SH: R
PCI: R
Command Log
These bits retain PCI command information (the state
of the C/
BE [3:0] line) when an error occurs.