31 plane n mode register (pnmr) (n = 1 to 6) – Renesas SH7781 User Manual
Page 925
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 895 of 1658
REJ09B0261-0100
19.3.31
Plane n Mode Register (PnMR) (n
= 1 to 6)
The plane n mode registers (PnMR, n = 1 to 6) set the display operation for plane n.
R/W:
Internal update:
R/W:
Internal update:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
R/W
R/W
R
R
R/W
R
R
R
R
R
R
R
R
R
R
R
O
O
O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PnWAE
PnTC
—
—
PnYCDF
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R
R
R/W
R/W
R
R/W
R/W
R/W
R
R
R/W
R/W
R
R/W
O
O
O
O
O
O
O
O
O
O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PnDDF
—
—
PnBM
—
PnDC
PnCPSL
—
—
PnSPIM
—
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value:
Bit Bit
Name
Initial
Value R/W
Internal
Update Description
31 to 21
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
20
PnYCDF
0
R/W
Yes
Plane n YC Data Format
0: Sets the order of YC data to UYVY format.
1: Sets the order of YC data to YUYV format.
19, 18
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
17
PnTC
0
R/W
Yes
Plane n Transparent Color
0: When set to 8 bits/pixel display, the
transparent color is the color set in the plane
n transparent color 1 register (PnTC1R)
1: When set to 8 bits/pixel display, any of the
transparent colors set in CP1TR to CP4TR
can be a transparent color
CP1TR to CP4TR to be used are determined
by the setting of the PnCPSL bit.
16
PnWAE
0
R/W
Yes
Plane n Wrap Around Enable
0: Wraparound is not performed for plane n
1: Wraparound is performed for plane n
15
⎯ 0
R
⎯ Reserved
This bit is always read as 0. The write value
should always be 0.