Renesas SH7781 - Manual (Page 100)

4. Pipelining
Rev.1.00 Jan. 10, 2008 Page 70 of 1658
REJ09B0261-0100
I1 I2 I3 ID s1 s2 s3 WB
I3
I3
I3
I3
I3
I3
I3
I1 I2 ID s1 s2 s3 WB
I1 I2 ID s1 s2 s3 WB
I1 I2 ID S1 S2 S3 WB
I1 I2 ID E1s1 E2s2 E3s3 WB
I1 I2 ID S1 S2 S3 WB
ID
ID
ID
I1 I2 ID E1S1 E2S2 E3S3 WB
ID
ID
ID
ID
ID
I1 I2 ID S1 S2 S3 WB
(I1) (ID) (I2) (I3)
(I1) (ID) (I2) (I3)
ID
ID
ID
ID
ID
ID
(4-1) LDC to Rp_BANK/SSR/SPC/VBR: 1 issue cycle
(4-2) LDC to DBR/SGR: 4 issue cycles
(4-3) LDC to GBR: 1 issue cycle
(4-4) LDC to SR: 4 issue cycles + 4 branch cycles
(4-5) LDC.L to Rp_BANK/SSR/SPC/VBR: 1 issue cycle
(4-6) LDC.L to DBR/SGR: 4 issue cycles
(4-7) LDC.L to GBR: 1 issue cycle
(4-8) LDC.L to SR: 6 issue cycles + 4 branch cycles
(Branch to the
next instruction.)
(Branch to the next instruction.)
Figure 4.2 Instruction Execution Patterns (4)