Renesas SH7781 - Manual (Page 205)

7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 175 of 1658
REJ09B0261-0100
SH = 0
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match,
ASIDs match, and
V = 1
Only one
entry matches
SR.MD?
Cache access
in write-through mode
Data TLB protection
violation exception
Initial page write
exception
Data TLB protection
violation exception
Cache access
in copy-back mode
EPR[5]? EPR[4]?
Data access to virtual address (VA)
VA is
in P4 area VA is
in P2 area VA is
in P1 area VA is in P0, U0,
or P3 area
Yes
Yes
No
No
No
Yes
Yes
Yes
No
1 (Privileged)
R/W? R/W?
0 (User)
D?
EPR[1]?
0 0
1
1
0
1 1
0
EPR[2]?
WT?
C = 1 and
CCR.OCE = 1
0
1
1
0
R W W R
MMUCR.AT = 1
Yes
No
Data TLB multiple
hit exception
Data TLB miss
exception
Memory access
(Non-cacheable)
Internal resource access
1
0
CCR.OCE?
1
0
CCR.CB?
0
1
CCR.WT?
VPNs match
and V = 1
1
0
CCR.OCE?
No
Figure 7.14 Flowchart of Memory Access Using UTLB (TLB Extended Mode)