Renesas SH7781 - Manual (Page 756)

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 726 of 1658
REJ09B0261-0100
Bus cycle
(Overrun 0, High level)
DRAK (High-active)
DACK (High-active)
Bus cycle
(Overrun 1, High level)
DRAK (High-active)
DACK (High-active)
Acceptance started
Accepted after one cycle of CLKOUT
at the falling edge of DACK
1st acceptance 2nd acceptance
: Non-sensitive period
Acceptance started
Accepted after one cycle of CLKOUT
at the rising edge of DACK
1st acceptance 2nd acceptance
CLKOUT
DREQ
CLKOUT
DREQ
CPU DMAC
CPU DMAC
Figure 14.20 Example 1 of DREQ Input Detection in Burst Mode Level Detection (Byte
Transfer in 8/16/32/64-Bit Bus Width, Word Transfer in 16/32/64-Bit Bus Width, or
Longword Transfer in 32/64-Bit Bus Width)