Renesas SH7781 - Manual (Page 1476)

28. General Purpose I/O Ports (GPIO)
Rev.1.00 Jan. 10, 2008 Page 1446 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
value R/W Description
0 P1MSEL0 0 R/W Out of the modules SCIF[3] and SCIF[4], and FLCTL,
selects the one which uses the pins
MODE4/SCIF3_TXD/FCLE,
MODE7/SCIF3_RXD/FALE, MODE8/SCIF3_SCK/FD0,
MODE9/SCIF4_TXD/FD1, MODE10/SCIF4_RXD/FD2,
and MODE11/SCIF4_SCK/FD3.
0: SCIF[3] and SCIF[4]
1: FLCTL
At power-on reset by the
PRESET pin, MODE4 and
MODE7 to MODE11 are selected.
Note: * When using the SIOF, SIOF selection of P1MSEL4 and P1MSEL3 and that of
P1MSEL12 and P1MSEL11 and P1MSEL6 and P1MSEL5 must be specified without
contradiction. The settings of the registers when the SIOF is used are shown in the
following: Correct operation of the SIOF cannot be guaranteed by the settings other
than the following.
Register Bit
Name
When the Following SIOF Pin Groups Are
Used:
SIOF_SCK/HAC0_BITCLK/SSIO_CLK
SIOF_MCLK/HAC_
RES
SIOF_SYNC/HAC0_SYNC/SSIO_WS
SIOF_RXD/HAC0_SDIN/SSIO_SCK
SIOF_TXD/HAC0_SDOUT/SSIO_SDATA
When the Following SIOF Pin Groups Are
Used:
DACK3/SCIF2_SCK/MMCDAT/SIOF_SCK
DACK2/SCIF2_TXD/MMCCMD/SIOF_TXD
SCIF2_RXD/SIOF_RXD
MODE5/SIOF_MCLK
MODE6/SIOF_SYNC
P1MSEL4, 3 B'00 is set. Other than B'00 is set.
P1MSEL12, 11 Other than B'01 is set. B'01 is set.
P1MSEL6, 5 Other than B'10 is set. B'10 is set.
P1MSEL1 B'0 is set. B'1 is set.