Renesas SH7781 - Manual (Page 861)

19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 831 of 1658
REJ09B0261-0100
Register Name Abbr.
Power-On
Reset by
PRESET
Pin/ WDT/
H-UDI
Manual
Reset by
WDT Sleep by
Sleep
Instruction
Module
Standby Deep
Sleep
Bits with
Internal Update
Function
Display timing generation registers
Horizontal display
start position
register HDSR Undefined Retained Retained Retained Retained All bits
Horizontal display
end position
register HDER Undefined Retained Retained Retained Retained All bits
Vertical display
start position
register VDSR Undefined Retained Retained Retained Retained All bits
Vertical display
end position
register VDER Undefined Retained Retained Retained Retained All bits
Horizontal scan
period register HCR Undefined Retained Retained Retained Retained All bits
Horizontal
synchronous pulse
width register HSWR Undefined Retained Retained Retained Retained All bits
Vertical scan
period register VCR Undefined Retained Retained Retained Retained All bits
Vertical
synchronous
position register VSPR Undefined Retained Retained Retained Retained All bits
Equivalent pulse
width register EQWR Undefined Retained Retained Retained Retained All bits
Separation width
register SPWR Undefined Retained Retained Retained Retained All bits
CLAMP signal start
position register CLAMPSR Undefined Retained Retained Retained Retained All bits
CLAMP signal
width register CLAMPWR Undefined Retained Retained Retained Retained All bits
DE signal start
position register DESR Undefined Retained Retained Retained Retained All bits
DE signal width
register DEWR Undefined Retained Retained Retained Retained All bits