Renesas SH7781 - Manual (Page 655)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 625 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
1, 0 SNPMD All 0 SH: R/W
PCI: —
Snoop Mode for PCICSAR0
These bits specify whether PCICSAR0 is compared
with the SuperHyway bus address requested by an
external device, or not. When PCICSAR0 is specified
to be compared, a condition to issue snoop
commands can be specified.
00: PCICSAR0 is not compared
01: Reserved (setting prohibited)
10: PCICSAR0 is compared. If the address matches
PCICSAR0 in the range, snoop commands are
not issued. If not, snoop commands are issued.
11: PCICSAR0 is compared. If the address matches
PCICSAR0 in the range, snoop commands are
issued. If not, snoop commands are not issued.
(25) PCI Cache Snoop Control Register 1 (PCICSCR1)
An external device can access memory of this LSI via the PCIC. When an PCI device accesses a
cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This register can
specify the function that uses PCICSAR1. For details, see section 13.4.4 (7), Cache Coherency.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R/W R/W R/W R/W
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SNPMD RANGE
R/W R R R R R R R R R R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — —
— — — — — — — — — — — — — — — —
— — — — — — — — — — — — — — — —
— — — — — — — — — — — — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value: