Renesas SH7781 - Manual (Page 824)

17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 794 of 1658
REJ09B0261-0100
17.5 Deep Sleep Mode
17.5.1 Transition to Deep Sleep Mode
If a SLEEP instruction is executed when the DSLP bit in SLPCR is set to 1, the chip switches
from the program execution state to deep sleep mode. The procedure for a transition to deep sleep
mode is as follows:
1. Make each modules stop by setting standby control registers MSTPCR0 and MSTPCR1 except
the H-UDI module, i.e. write H’3F33 330C to MSTPCR0 and write H’0002 0031 to MSTPCR1.
For the note of the transition to module standby mode, see section 17.6.1, Transition to Module
Standby Mode and each module sections.
2. Execute a SLEEP instruction when the DSLP bit in SLPCR.
After execution of the SLEEP instruction, the CPU halts but its register contents are retained. The
DU is stopped* as well as the modules that were stopped by the module standby function. Except
for the DMAC, peripheral modules continue to operate. The clock continues to be output to the
CKIO pin, but all bus access (including auto refresh) stops. When using memory that requires
refreshing, select self-refreshing mode prior to making the transition to deep sleep mode.
Note: * For the transition to deep sleep mode of the DU, PCIC, LBSC and DBSC, see notes of
the transition to deep sleep mode in each module sections.
In deep sleep mode, a high-level signal is output at the STATUS1 pin, and a low-level signal at
the STATUS0 pin.
When using the PCIC, it is prohibited to make a transition to deep sleep mode. If transition to deep
sleep mode, the operation of the PCIC is not guaranteed.
If making a transition to deep sleep mode while each modules are in operation, the results of those
operation cannot be guaranteed.