Renesas SH7781 - Manual (Page 630)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 600 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Description
6 SDI 0 SH: R/WC
PCI: R
SERR Detection Interrupt
Indicates that the assertion of
SERR was detected
when the PCIC is a host.
0: A
SERR detection interrupt was not generated
1: A
SERR detection interrupt was generated
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
5 DPEITW 0 SH: R/WC
PCI: R
Data Parity Error Interrupt in Target Write
Indicates that a data parity error was detected in
reception of a target write transfer when the PCIC is
a target.
Note: A data parity error in target write is detected
only when bit 6 (PER) in PCICMD is set to 1.
0: A data parity error interrupt was not generated in
target write
1: A data parity error interrupt was generated in
target write
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.
4 PEDITR 0 SH: R/WC
PCI: R
PERR Detection Interrupt in Target Read
Indicates that
PERR was received in reception of a
target read transfer when the PCIC is a target.
Note:
PERR is detected in target read only when bit
6 (PER) in PCICMD is set to 1.
0: A
PERR detection interrupt was not generated in
target read
1: A
PERR detection interrupt was generated in
target read
When TTADI bit is write to 0, target target-abort
interrupt is cleared. When write to 1, it is not
available.