Renesas SH7781 - Manual (Page 628)

13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 598 of 1658
REJ09B0261-0100
(6) PCI Interrupt Register (PCIIR)
PCIIR records interrupt sources. When an interrupt occurs, the corresponding bit is set to 1. When
multiple interrupts occur, only the first source is registered. When an interrupt is disabled, 1 is
written to the corresponding bit by the interrupt source, and no interrupt occurs.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit:
Initial value:
R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R/WC R R R R R R/WC
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MRD
PEI
MW
PDI
MAD
IM
TAD
IM
PEDI
TR
DPEI
TW
SDI
APE
DI MDEI
TMT
OI
— — — — —
TTA
DI
R R R R R R R R R R R R R R R R
R R R R R R R R R R R R R R R R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
— — — — — — — — — — — — — — — —
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Description
31 to 15
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
14 TTADI 0 SH: R/WC
PCI: R
Target Target-Abort Interrupt
Indicates that the PCIC has terminated a transaction
with a target-abort when the PCIC functions as a
target.
A target-abort is detected as an illegal byte enable
when the lower two bits (bits 1 and 0) of the address
and the byte enable do not match during an I/O
transfer (target).
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
13 to 10
⎯
All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.