Renesas SH7781 - Manual (Page 819)

17. Power-Down Mode
Rev.1.00 Jan. 10, 2008 Page 789 of 1658
REJ09B0261-0100
17.3.3 Standby Control Register 1 (MSTPCR1)
MSTPCR1 is a 32-bit readable/writable register that each module of H-UDI, UBC, DMAC, and
GDTA operates or is stopped. MSTPCR1 can be accessed only in longword.
This register is initialized by a power-on reset by the
PRESET pin or power-on reset by WDT
overflow, or H-UDI reset.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯
MSTP117
⎯
MSTP119
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSTP100
⎯ ⎯ ⎯
MSTP[105:104]
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 20
⎯ All
0 R/W Reserved
These bits are always read as 0. The write value
should always be 0.
19 MSTP119 0 R/W Module Stop Bit 119
Specifies that the clock supply to the H-UDI module is
stopped
0: H-UDI operates
1: H-UDI stopped
18
⎯
0 R/W Reserved
These bits are always read as 0. The write value
should always be 0.
17 MSTP117 0 R/W Module Stop Bit 117
Specifies that the clock supply to the UBC module is
stopped
0: UBC operates
1: UBC stopped