Renesas SH7781 - Manual (Page 1137)

22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1107 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
8 RXE 0 R/W Receive Enable
0: Disables data reception from SIOF_RXD
1: Enables data reception from SIOF_RXD
• This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
• When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOF_RXD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
• This bit is initialized by a receive reset.
7 to 2
⎯ All
0 R Reserved
These bits are always read as 0. The write value should
always be 0.
1 TXRST 0 R/W Transmit Reset
0: Does not reset transmit operation
1: Resets transmit operation
• This bit setting becomes valid immediately. For
details on initialization, see section 22.4.7 (5),
Transmit/Receive Reset.
• This bit is automatically cleared by SIOF after
completes a reset, to be always read as 0.
0 RXRST 0 R/W Receive Reset
0: Does not reset receive operation
1: Resets receive operation
• This bit setting becomes valid immediately. For
details on initialization, see section 22.4.7 (5),
Transmit/Receive Reset.
• This bit is automatically cleared by SIOF after
completes a reset, to be always read as 0.