Renesas SH7781 - Manual (Page 1010)

20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 980 of 1658
REJ09B0261-0100
20.3.2 GA Enable Register (GACER)
GACER is in the GDTA common register block and controls the block operation.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt:
Initial value:
R/W:
0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CL_EN MC_EN
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
R/W R/W ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 2
⎯
All 0
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
1 MC_EN 0 R/W Enables access to the MC registers.
0: Writing to the MC registers is invalid. The value read
from the MC register is undefined.
1: Reading and writing are enabled.
0 CL_EN 0 R/W Enables access to the CL registers.
0: Writing to the CL registers is invalid. The value read
from the CL register is undefined.
1: Reading and writing are enabled.